Itanium
From Wikinfo
In computing, the Itanium is a 64-bit microprocessor architecture, developed jointly by Hewlett-Packard and Intel. The goal of Itanium is to produce a "post-RISC era" high performance architecture using a very long instruction word (VLIW) design. Its native instruction set is the new IA-64, but it can run x86 code (slowly) in a firmware emulation mode, and has hooks for PA-RISC family migration.
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Design
At the most basic level the Itanium design is similar to RISC -- the core logic consists of a small set of instructions that are designed to run very fast. The Itanium uses a superscalar design, that is, several cores running in parallel for extra speed. Where the Itanium breaks with current RISC design philosophy is in how it feeds instructions into those core units.
The design is centred on Explicitly Parallel Instruction Computing (EPIC), similar to VLIW design, but with a number of enhancements. Where a typical VLIW will assign sub-instructions from each long instruction word to a particular fixed functional unit, the Itanium supports several bundle mappings to allow for more instruction mixing possibilities and which include a balance between serial and parallel execution modes. There was room left in the initial bundle encodings to add more mappings in future versions of IA-64. In addition, the Itanium has individually settable predicate registers to cause a kind of runtime determined "no output" mode to each instruction.
Early Implementation
Design of the Itanium series started in 1994, based on pioneering research by Hewlett-Packard into VLIW designs. The original HP design was "clean", but that is to be expected from a design that was never to be used in a production setting. After Intel became involved the cleanliness of the original design was marred by the addition of several new capabilities needed for "real work" use, notably the ability to run IA-32 instructions, and HP adding their own features to ease migration from the HP-PA.
The project has met with lackluster market success. Originally planned for release in 1997, the schedule slipped several times. In 2001 the first version, code named Merced shipped. Speeds of 733 and 800MHz were offered, with a choice of 2Mb or 4Mb cache. Prices ranged from US$1200 to over US$4000. However, performance was disappointing. In IA-64 mode, it performed only slightly better than an equivalently clocked x86 design, and when running x86 code, performance was extremely poor, about 1/8th that of an similarly clocked x86 processor. Soon even Intel suggested it wasn't a "real" release.
The main (though by no means only) problem with the Itanium was that the latency of its third-level cache was extremely high, which resulted in the amount of usable bandwidth being greatly reduced. Intel was forced to use an on-die solution for the next design, and at the same time lowered the primary and secondary cache latencies to the lowest of any modern design (apart from IBM's POWER4). They also upgraded the Itanium's 64-bit 266MHz bus to a 128-bit 400MHz bus, tripling system bandwidth.
Itanium2
The second generation Itanium chips (Itanium 2) were launched in July 2002. In IA-64 mode, Integer performance was the best out of any design at the time of launch, while Floating-point code was second only to Power4 (IBM Power). Available models were 1Ghz with 3MB L3 cache and 900Mhz with 1.5MB L3 cache. Unfortunately, x86 performance, while improved, was still much slower than that of current x86 processors; Itanium 2's performance is similar to that of a Pentium II at 2/3 the clock speed.
Approximately one year later the second revision of the Itanium 2 design was released. Available versions are 1.5Ghz with 6MB L3, 1.4 Ghz with 4MB, and 1.3Ghz with 3MB. At the time of release, the 1.5Ghz version posted the highest uniprocessor SpecFP and SpecInt scores of any shipping chip.
In Q3 2003, a low-cost Itanium2 at 1.4Ghz with 1.5 MBL3 and a low power version at 1Ghz with 1.5MB L3 cache were launched. The former was targeted to workstations, lower-end servers, and HPC clusters, while the latter was targeted to blade servers and other "dense" computers. In Q4 2003, Intel stopped the production of the older 0.18 micrometre Itanium 2 processors (900MHz and 1GHz models).
In Q2 2004, Intel launched a low cost 1.4GHz/3MB processor at the same price as the existing 1.4GHz/1.5MB processor, deprecating the latter. Also in Q2 2004, Intel launched a 1.6GHz Itanium 2 with 3MB L3, the highest clockrate Itanium 2 available at the time.
Software
While some efforts have been made to improve the execution speed of x86 code, it remains too slow for some purposes. The importance of the x86 functionality is debatable — not many people are buying Itanium systems to run x86 code on. Indeed, Intel plans to replace the hardware x86 translation unit with a software emulation package (in the spirit of Digital's FX!32 for DEC Alpha). Faster execution and decreased chip complexity are expected. Software legacy-processor emulation has precedent in enterprise computing, being used in VAX and S/390 machines, among others.
Software support has much improved since the release of the Itanium 2. Ported operating systems include HP-UX, Linux, and Microsoft Windows. OpenVMS and FreeBSD are being worked on. HP eventually wants to move Tru64 customers to HP-UX on Itanium rather than porting it. Oracle and DB/2 ports are available, among others.
Concerns
In 2002, the Itanium was the second most expensive computing project in history, behind only the IBM 360 (which, it's important to note, was a huge success). Nevertheless there remain some doubts about the future of the product, centering mainly on two problems.
The first is that the benefits in simplicity, one of the main goals of the VLIW design, are not at all evident in the Itanium. Despite the fact that its core contains fewer transistors than a Pentium 4, the 2nd generation Itanium has a massive 221 million transistors drawing an equally massive 130 watts of power (max). In 2003 Intel began to address the problem of power consumption by introducing low-voltage Itanium 2 processors which consume a maximum of 60 watts (with the obvious tradeoffs of lower clock speed and smaller L3 cache). The bulk of the Itanium's transistor count is in the form of on-die cache which drives the microchip's complex, three-level cache subsystem. According to the 2004 roadmap, Intel plans to expand the L3 cache in the main Itanium line, following a natural trend in performance microchip designs. The low-voltage Itanium line will retain conservative cache sizes for the near future.
Designing a compiler which allows the Itanium to perform up to its potential has proved to be a difficult task and a very serious issue. Nevertheless, improvements are steadily being made; there are a number of Itanium compiler projects such as ORC and Impact.
Critics of the Itanium processor have labeled it the "Itanic". Intel will be in a difficult position if the Itanium processor is a disappointment, as the need for 64-bit architecture in commodity servers is now pressing, and the need for a 64-bit architecture in personal computers is only a few years away. Intel insists that the Itanium currently targets a niche-market. Both Intel and HP have maintained their support of the platform and it's future viability. HP in particular continues to follow through with the phase-out of the PA-RISC and Alpha architectures.
A number of other CPU lines have been end-of-lifed in favor of Itanium. HP's DEC Alpha and PA-RISC family lines are being retired in favor of Itanium hardware. HP plans to continue support for the older lines for about 5 years as of 2003. SGI originally intended to phase out its MIPS architecture CPUs in favor of Itanium as soon as possible, but its plans are now unclear and a two-architecture product line is likely for the near future. SGI's Itanium line is doing well, but its IRIX technology and installed base are significant.
Future Roadmap
The next step for the Itanium family is expected to be a 0.13 micrometre Itanium2 with 9MB L3 cache at around 1.8Ghz. A version of this chip will likely use a 667Mhz FSB. After that, a dual-core, 24MB L3 cache, 1.7 billion transistor design codenamed Montecito is expected in 2005, to be manufactured on a 90nm process. This line will see incremental speed gains and low-voltage versions until it is followed in perhaps 2007 by a chip codenamed Tukwila which is being designed by many of the engineers from the cancelled Alpha EV8 project and which could outperform the current (1.3 Ghz and up) Itanium 2 by a factor of 10.
AMD64
A possible architectural threat to Intel now exists in the form of AMD's AMD64 architecture. AMD's AMD64 follows Intel's earlier behavior of extending a single architecture, from the 8-bit 8080 to the 16-bit 8086, then from 16-bits to the 32-bit 80386 and beyond, without ever removing backwards compatibility. The AMD64 architecture further extends the 32-bit x86 architecture by adding 64-bit registers, with a full 32-bit and 16-bit compatibility modes for earlier software. AMD64 systems began shipping in the middle of 2003.
Performance is very good, but the processor, called the Opteron, appears to be more of a competitor to Intel's 32-bit server chips — the largest non-clustered systems currently being shipped have 4 processors (versus Itanium 2's 256) and the only native 64-bit server OS support currently available for them are Linux, NetBSD, OpenBSD and FreeBSD.
With AMD64's adoption by manufacturers such as Sun Microsystems and Hewlett-Packard, Intel released the IA-32e, which is fully instruction-set compatible with the AMD64, in February 2004.
References
- Adapted from the Wikipedia article, "Itanium" http://en.wikipedia.org/wiki/Itanium, used under the GNU Free Documentation License
